PIC16C63A-20/SS【PDF 44/184 页】IC MCU OTP 4KX14 PWM 28SSOP

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138

SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data field, a 5-bit address

field and a read/write bit. The data to be written is scanned into the 32-bit data field with the address of the register

to the 5-bit address field and 1 to the read/write bit. A register is read by scanning its address into the address field

and 0 into the read/write bit, going through the UPDATE-DR TAP state, then scanning out the data.

Refer to the ARM7TDMI reference manuel for more information on Comm channel operations.

Figure 20-8. TAP 8-bit DR Register

A read or write takes place when the TAP controller enters UPDATE-DR state. Refer to the IEEE 1149.1 for more

details on JTAG operations.

The address of the Debug Comms Control Register is 0x04.

The address of the Debug Comms Data Register is 0x05.

The Debug Comms Control Register is read-only and allows synchronized handshaking between the processor

and the debugger.

– Bit 1 (W): Denotes whether the programmer can read a data through the Debug Comms Data Register.

If the device is busy W = 0, then the programmer must poll until W = 1.

– Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms Data Register. If R

= 1, data previously placed there through the scan chain has not been collected by the device and so

the programmer must wait.

The write handshake is done by polling the Debug Comms Control Register until the R bit is cleared. Once cleared,

data can be written to the Debug Comms Data Register.

The read handshake is done by polling the Debug Comms Control Register until the W bit is set. Once set, data

can be read in the Debug Comms Data Register.

20.3.4

Device Operations

Several commands on the Flash memory are available. These commands are summarized in Table 20-3 on page

126. Commands are run by the programmer through the serial interface that is reading and writing the Debug

Comms Registers.

TDI

TDO

r/w

Address

Data

Address

Decoder

Debug Comms Control Register

Debug Comms Data Register

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